IBM System z - z10

Enterprise Class - 2097

Released on February 26, 2008, the System z10 Enterprise Class is available in five hardware models: E12, E26, E40, E56, and E64. Each are of the machine type 2097. The Enterprise Class PU cores (four per chip) operate at speeds of 4.4 GHz, still (December, 2008) the highest clock speed of any processor with more than two cores per chip. The processors are stored in one to four compartments referred to as "books". Each book is comprised of a multi-chip module (MCM) of processing units (PUs) and memory cards (including multi-level cache memory). The number of PUs in each book is based upon the model number:

 

Model

Books / PUs

CPs

IFLs / uIFLs

ICFs

Opt SAPs

Standard Memory (GB)

Flexible Memory (GB)

E12

1 / 17

0-12

0-12 / 0-11

0-12

0-3

16 - 352

NA

E26

2 / 34

0-26

0-26 / 0-25

0-16

0-7

16 - 752

32 - 352

E40

3 / 51

0-40

0-40 / 0-39

0-16

0-11

16 - 1136

32 - 752

E56

4 / 68

0-56

0-56 / 0-55

0-16

0-18

16 - 1520

32 - 1132

E64

4 / 77

0-64

0-64 / 0-63

0-16

0-21

16 - 1520

32 - 1136

 

NOTES:
A minimum of one CP, IFL, or ICF must ordered with every model.
For each CP ordered, one zAAP and one zIIP may also be ordered.
Optional SAPs are required only in some situations when using TPF/ESA or z/TPF.
Memory figures refer to user-accessible memory. The z10 EC reserves 16GB for HSA (Hardware System Area).
Sub-capacity (fractional) CP configurations are also available.

 

Business Class - 2098

Released on October 21, 2008, the z10 Business Class has only a single model: E10. Machine type is 2098. It has the same processor chip design and instruction set as the z10 EC but with higher manufacturing yields (3.5 GHz clock speed, one core per chip disabled) and lower cost processor packaging due to reduced cooling and reduced multi-chip shared cache needs. The z10 BC also introduced new, more efficient I/O packaging options. It is possible to configure a z10 BC without spare cores if desired, although such maximally configured z10s still fail gracefully in the unlikely event there's a core failure: the system will move any work from the failed core to surviving cores automatically, without operating system or software involvement, keeping all applications running, albeit at slightly reduced capacity if there are no spares remaining.

 

Model

CPs

IFLs

ICFs

Standard Memory (GB)

E10

1-5

1-10

1-10

4 - 120 (-248 in June, 2009)